PLL (Phase-Locked Loop) has been used as a clock synthesizer in various fields such as wireless transmission/reception apparatuses, clock data recovery systems, and processors. PLL includes a phase comparator, a loop filter, a voltage controlled oscillator, and a divider, as basic configuration elements.
PLL used in the wireless apparatuses and the like is demanded to generate a high-frequency clock signal with high accuracy. For example, with regards to WiMAX and GSM1800, it is demanded to keep the frequency of 2.5 GHz within an allowable range of 130 Hz.
On the other hand, with respect to a digital PLL, the digital signal of a reference frequency is inputted, and an oscillator generates a high-frequency output signal based on a digital control signal outputted from a loop filter, and the digital signal having the frequency of the high-frequency output signal is fed back to a phase comparator. Thus, there have been attempts to apply digital circuits to all the elements except for the oscillator. For example, the digital PLL is disclosed by the following patent documents (Japanese Unexamined Patent In the digital PLL, the frequency of the oscillator is controlled based Application Publication No. 11-31971; Japanese Unexamined Patent Application In the digital PLL, the frequency of the oscillator is controlled based Publication No. 2008-136202) and a non-patent document (“A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme.” IEEE JOURNAL OF SOLID-STATE CIRCUITS, volume 43, no. 11, November 2008).